This invention relates to high speed analog signal acquisition. More particularly, this invention relates to circuits and methods for increasing the number of samples of an analog signal acquired in response to respective primary strobe clock signals by inserting between those primary clock strobe signals secondary strobe signals having a controlled phase delay with respect to the primary strobe signals.
In known Fast In, Slow Out ("FISO") digitizers, the highest sampling rate of an incoming analog signal is determined by a delay line comprising a series of buffers, where each buffer introduces a delay and wherein the total delay of all the buffers is forced by a control system to equal the period of a reference clock. The series of buffers is referred to as a "timing chain." The output of each buffer provides a strobe signal used to acquire a sample of an analog signal at a unique point in time.
The average delay of the buffers can reliably be tuned to a minimum of about 500 picoseconds using a 1 micron CMOS fabrication process, which, for a series of 33 buffers, results in a maximum of about 2 Gigasamples per second ("GS/s"). However, to achieve the same sample rate at substantially more than 33 samples, or to achieve higher sample rates with the same number of samples, the timing chain approach has been found to be inadequate.
For example, it is known that the sampling rate of a timing chain can be doubled by connecting two buffers in parallel to the output of each buffer in the series, the two parallel buffers having different signal delays and providing the strobe signals. However, an increase of the overall sampling rate above 2 GS/s is still not made practical by this approach because of limitations on the accuracy and stability of the delays introduced by the individual buffers in the chain.
In addition, although the sum of buffer delays is kept correct, individual delays are usually inconsistent, resulting in non-uniformly sampled data. When sampling high-speed analog inputs with bandwidths as high as 1 Ghz, timing errors on the order of a few picoseconds become significant in an 8-bit representation of the acquired signal.
There are two techniques known to be applied to this problem. One is to use microprocessor software to correct the sampled data, wherein a digital signal processing ("DSP") algorithm is applied to make the non-uniformly sampled data nearly uniform in time. Another is to correct the individual delays of the timing chain using hardware. Both techniques require that (1) the individual delays, though not equal to one another, be at least substantially constant in time, and (2) the individual delays, though constant in time, do not vary so much from one another that adjacent samples overlap. If the delays do change significantly, a lengthy calibration process must be invoked whether software or hardware correction is used.
Accordingly, there is a need for a novel method and circuit architecture for high speed sampling of analog signals to obtain uniformly spaced samples at rates in excess of 2 GS/s without the need for frequent, lengthy calibration of the signal sampling system.